Interrupts in 8085 Microprocessor: Vectored-Non Vectored Interrupts And Maskable-Non Maskable Interrupts

Vectored Interrupt:

In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control is to be transferred. the processor automatically branches to the specific address in response to an interrupt. 

• The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.

Non-Vectored Interrupt: 

But in non-vectored interrupts the interrupted device should give the address of the interrupt service routine (ISR).   

• The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR after receiving interrupt acknowledge signal.

Maskable & Non-Maskable Interrupt:

The hardware vectored interrupts are classified into maskable and non-maskable

interrupts. 

• TRAP is non-maskable interrupt. 

• RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt. Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked the processor will not accept the interrupt signal. The interrupts can be masked by moving an appropriate data or code to accumulator and

then executing SIM (Set Interrupt Mask) instruction. The status of maskable interrupts can be read into accumulator by executing RIM (Read Interrupt Mask) instruction. All the hardware interrupts, except TRAP are disabled, when the processor is resetted. They can also be disabled by executing Dl (Disable Interrupt) instruction.

• When an interrupt is disabled, it will not be accepted by the processor. (i.e., INTR, RST 5.5, RST 6.5 and RST 7.5 are disabled by DI instruction and upon hardware reset). • To enable (to allow) the disabled interrupt, the processor has to execute El instruction (El-Enable Interrupt). The type of signal that has to be placed on the interrupt pin of hardware interrupts of 8085 are defined by INTEL.

• The TRAP interrupt is edge and level sensitive. Hence, to initiate TRAP, the interrupt signal has to make a low to high transition and then it has to remain high until the interrupt is recognized.

• The RST 7.5 interrupt is edge sensitive (positive edge). To initiate the RST 7.5, the interrupt signal has to make a low to high transition an it need not remain high until it is recognized.

• The RST 6.5, RST 5.5 and INTR are level sensitive interrupts. Hence for these interrupts the interrupting signal should remain high, until it is recognized.