Skip to main content

Interrupts in 8085 Microprocessor-Hardware Interrupt And Software Interrupt

  • What is Interrupt and how it is generated?

Interrupt is a signal send by an external device to the processor, to the processor to perform a particular task or work. In the microprocessor based system the interrupts are used for data transfer between the peripheral and the microprocessor. When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate signal to the interrupt pin of the processor. If the processor accepts the interrupt then the processor suspends its current activity and executes an interrupt service subroutine to complete the data transfer between the peripheral and processor. After executing the interrupt service routine the processor resumes its current activity. This type of data transfer scheme is called interrupt driven data transfer scheme.

  • Types Of Interrupt:

The interrupts are classified into software interrupts and hardware interrupts.

• The software interrupts are program instructions. While running a program, if a software interrupt instruction is encountered, then the processor executes an interrupt service routine (ISR).

• The hardware interrupts are initiated by an external device by placing an appropriate signal at the interrupt pin of the processor. If the interrupt is accepted, then the processor executes an interrupt service routine (ISR).

• Software Interrupts:

The software interrupts are program instructions. When the instruction is executed, the processor executes an interrupt service routine stored in the vector address of the software interrupt instruction. The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and RST 7. The vector addresses of software interrupts are:

The software interrupt instructions are included at required place in the main program. When the processor encounters the software instruction, it pushes the content of Program Counter to stack. Then loads the Vector address in program counter and starts executing the Interrupt Service Routine (ISR) stored in this vector address. At the end of ISR, a return instruction RET will be placed. When the RET instruction is executed, the processor POP the content of stack to program counter. Hence the processor control returns to the main program after servicing the interrupt. All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be masked and they cannot be disabled.

• Hardware Interrupts:

An external device, initiates the hardware interrupts of 8O85 by placing an appropriate signal at the interrupt pin of the processor. The processor keeps on checking the interrupt pins at the second T -state of last machine cycle of every instruction. If the processor finds a valid interrupt signal and if the interrupt is unmasked and enabled, then the processor accepts the interrupt. Then microprocessor sends acknowledgement by an INTA signal to the interrupted device. The processor saves the content of program Counter in stack and then loads the vector address of the interrupt in PC. If the interrupt is nonvectored, then the interrupting device has to supply the address of ISR when it receives INTA signal. It starts executing ISR in this address. At the end of ISR, a return instruction, RET will be placed. When the processor executes the RET instruction, it POP the content of top of stack to PC. Thus the processor control returns to main program after servicing interrupt. The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR. The address of hardware interrupts are:

• Vectored-Non Vectored Interrupts And Maskable-NonMaskable Interrupts:

If you are interested to know more on any other subject in which you are interested or if you have any doubts then tell us in comment about it.  





Comments

Popular posts from this blog

8085 Microprocessor: De-multiplexing of AD0-AD7 Address and Data Lines

  De-multiplexing of AD0-AD7 of 8085 Microprocessor THE ADDRESS AND DATA BUSES: • 8085 Microprocessor have total 16 address lines and 8 data lines. • 8 signal lines A8 – A15 which are unidirectional. • The other 8 address bits are multiplexed with the 8 data bits. So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 (address bus) and D0 – D7 (data bus) at the same time. • During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes. THE CONTROL AND STATUS SIGNALS: • There are 4 main control and status signals. 1. ALE (Address Latch Enable): This signal is a pulse that become 1 when the AD0 –AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. 2. RD (Rea

Interrupts in 8085 Microprocessor: Vectored-Non Vectored Interrupts And Maskable-Non Maskable Interrupts

Vectored Interrupt: In vectored interrupts, the manufacturer fixes the address of the ISR to which the program control is to be transferred. the processor automatically branches to the specific address in response to an interrupt.  • The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts. Non-Vectored Interrupt:   But in non-vectored interrupts the interrupted device should give the address of the interrupt service routine (ISR).    • The INTR is a non-vectored interrupt. Hence when a device interrupts through INTR, it has to supply the address of ISR after receiving interrupt acknowledge signal. Maskable & Non-Maskable Interrupt: The hardware vectored interrupts are classified into maskable and non-maskable interrupts.  • TRAP is non-maskable interrupt.  • RST 7.5, RST 6.5 and RST 5.5 are maskable interrupt. Masking is preventing the interrupt from disturbing the main program. When an interrupt is masked the processor will not accept the interrupt signal. The interrupts ca